1. Field
This disclosure relates to semiconductor devices and, specifically to high power semiconductor devices fabricated on silicon carbide substrates.
2. Related Arts
Semiconductor SiC can be used to build semiconductor devices that operate at voltages in the range of 600-10000V and higher. Crystalline originated defects such as micropipes, screw dislocations and basal plane dislocations are present in significant quantities in SiC substrates and will become incorporated into the active region of a semiconductor device made with this material. The defects alone and together are believed to be limiting the operational performance and stability of semiconductor SiC devices with respect to that predicted from theory, and the effects of these defects become more pronounced when the devices are designed to operate at very high end of the voltage range.
Silicon carbide, SiC, is a crystalline semiconductor material, recognized by those familiar with materials science, electronics and physics as being advantageous for wide band gap properties and also for extreme hardness, high thermal conductivity and chemical inert properties. These properties make SiC a very attractive semiconductor for fabrication of power semiconductor devices, enabling power density and performance enhancement over devices made from more common materials like silicon. There are many published summaries of the properties of SiC. For example, the properties of SiC are compiled by the Ioffe Institute and published online as “Electronic archive. New Semiconductor Materials. Characteristics and Properties.” (1998-2001). Common SiC materials constants values published by Ioffe are often used in device modeling activities. See, also, “Handbook Series on Semiconductor Parameters” vol. 1, 2 edited by M. Levinstein, S. Rumyantsev and M. Shur, World Scientific, London, 1996, 1999.
The most common forms of SiC consist of cubic or hexagonal arrangements of atoms. The stacking of Si and C layers can take on many forms, known as polytypes. The type of silicon carbide crystal is denoted by a number denoting the number of repeat units in the stacking sequence followed by a letter representing the crystalline format. For example the 3C-SiC polytype refers to a repeat unit of 3 and a cubic (C) lattice, while a 4H-SiC polytype refers to repeat unit of 4 and a hexagonal (H) lattice.
The different silicon carbide polytypes have some variations in materials properties, most notably electrical properties. The 4H-SiC polytype has the relatively larger bandgap while the 3C-SiC has a smaller bandgap, with the bandgaps for most other polytypes falling in between. For high performance power device applications when the bandgap is larger, the material is more capable, in theory, to offer relatively higher high power and thermal conductivity performance.
SiC crystals do not occur in nature and as such must be synthesized. Growth of SiC crystals can be executed by sublimation/physical vapor transport or chemical vapor deposition.
Growth of SiC by sublimation is very challenging. Temperatures in excess of 2000° C. are required to generate as vapor stream of Si/C species by sublimation, which places great limitations on the reaction cell components and the furnace design. Originally SiC abrasive materials formed by processes like the Acheson method were used as the source of the Si and C atoms for the crystal, and as the technology matured groups developed means to synthesize SiC source powder specifically for SiC crystal growth. The growth is usually performed in a graphite container within a vacuum chamber. The graphite container is heated by either resistive methods or induction methods. The container is insulated in a careful manner as to create controlled temperature gradients within the volume. A seed crystal is used and usually shaped like a plate or disc. The seed crystal is typically oriented with its growth surface facing the source material. The location of the seed crystal in the container is designed such that when the container is heated the seed is at a relatively lower temperature position, while the Si—C source materials are at the higher temperature position. When the container is heated to a temperature sufficient to sublime the source material, the vapors will travel towards the low temperature region and condense on the seed crystal. While this appears simple in concept, in practice the growth of SiC is very complicated and recognized by those who practice as very difficult to perform.
Historically, initial progress in SiC sublimation-based crystal growth is described first by Lely (U.S. Pat. No. 2,8543,64—1958) whose method of unseeded crystal growth resulted in small hexagonal SiC platelets. In the 1970s and 1980s the art to produce the first crystals of size attractive for producing devices was done in Russia by Tairov and Tsvetkov (Journal of Crystal Growth, 52 (1981) p. 146-50 and Progress in Controlling the Growth of Polytypic Crystals in Crystal Growth and Characterization of Polytype Structures, P. Krishna, ed., Pergammon Press, London, p. 111 (1983)). Their approach used a Lely crystal as a seed, and conducted growth by sublimation and transport as described above. These results showed methods for polytype control by choice of seeds, pressure control and temperature gradients. Later, Davis (U.S. Pat. No. 4,866,005—1989) revealed improvements by judicious selection of source materials and gradient controls. Refinements on the methods of Tairov, Tsvetkov and Davis continue to be revealed to this day.
When methods to produce larger crystals emerged, focus also moved to control defects in the crystals. Defects can be categorized as inclusions and crystal dislocations. The primary crystalline defects in SiC crystals are screw dislocations. Among these are a special case known as a micropipe or hollow core screw dislocations. Additionally, there are basal plane dislocations and threading edge dislocations. These defects originate from many sources. For example, defects contained in the seed crystal can be passed to the newly grown crystal volume. Stresses arising from temperature gradients and thermal expansion mismatch and imparted to the seed and crystal during growth can result in formation of dislocations. Deviation of the stoichiometry in the sublimation vapor stream from that needed to form SiC can result in unstable polytype growth—in turn leading to polytype inclusions in the grown crystal, which lead to dislocation formation at the polytype boundaries. Even interactions between dislocations can create or eliminate dislocations.
SiC crystals produced by methods identified have large concentrations of dislocations. As of this filing, the commonly reported values of screw dislocation and basal plane concentration are nominally 5000-10000/cm2, respectively. The dislocations are most commonly assessed by sectioning the crystal in the plane normal to the crystal axis of symmetry. Etching the exposed crystal surface with molten salt, like potassium hydroxide, at temperatures in the 350-500° C. range will reveal the dislocations which cross the plane of the substrate. Each dislocation type has a unique shape so they can be uniquely counted. The dislocations are commonly counted and reported as a number divided by the inspection area. This characterization method is useful as it allows for easy identification of defects revealed by etching which are present in the active region of semiconductor devices formed on the substrate plane. These defects, or the lack thereof, are often correlated with the electrical operation parameters of the device. There are many examples in the literature which show that dislocations are not uniformly distributed. The large count of dislocations makes it very impractical to count every single one, especially as today inspections can be required on sections greater than or equal to the equivalent of 100 mm diameter circles. So while the entire substrate area may be etched, only the limited part of the surface which is sampled for inspection will determine the amount of dislocations assigned to the part. Incorrect sampling methods can lead to errors in the estimation of the dislocation concentration associated with larger crystals. In most reports, the details of the sampling method are not provided, so replication of results can often be difficult, if not impossible.
Scientists experienced in solid state physics and semiconductor devices know that dislocations result in device performance below the theoretical properties of the material. Therefore modern effort focused on improvements of semiconductor SiC crystal quality look to identify and control the factors which can reduce defects originating in crystal growth.
Once large enough crystals are produced the crystal must be cut and fabricated into wafers in order to be useful in devices to fabricate semiconductor devices using planar fabrication methods. As many semiconductor crystals (e.g., silicon, gallium arsenide) have been successfully developed and commercialized into wafer products the methods to fabricate wafers from bulk crystals are known. A review of the common approaches to, and requirements for wafer fabrication and standard methods of characterization can be found in Wolf and Tauber, Silicon Processing for the VLSI Era, Vol. 1—Process Technology, Chapter 1 (Lattice Press—1986).
Due to its hardness, fabrication of SiC into wafer substrates presents unique challenges compared to processing other common semiconductor crystals like silicon or gallium arsenide. Modifications must be made to the machines and the choices of abrasives changed beyond commonly used materials. The modifications made on common wafer fabrication techniques in order to accommodate SiC are often kept as proprietary information by their inventors. It has been reported that substantial subsurface damage is observable on mirror polished SiC wafers, and this can be reduced or removed by using chemical enhanced mechanical polishing methods similar to that used in the silicon industry (Zhou, L., et al., Chemomechanical Polishing of Silicon Carbide, J. Electrochem. Soc., Vol. 144, no. 6, June 1997, pp. L161-L163).
In order to build semiconductor devices on SiC wafers additional crystalline SiC films must be deposited on the wafers to create the device active regions with the required conductivity value and conductor type. This is typically done using chemical vapor deposition (CVD) methods. Techniques for growth of SiC by CVD epitaxy have been published from groups in Russia, Japan and the United States since the 1970's. The most common chemistry for growth of SiC by CVD is a mixture of a silicon containing source gas (e.g., monosilanes or chlorosilanes) and a carbon containing source gas (e.g., a hydrocarbon gas). A key element to growth of low defect epitaxial layers is that the substrate surface is tilted away from the crystal axis of symmetry to allow the chemical atoms to attach to the surface in the stacking order established by the substrate crystal. When the tilt is not adequate the CVD process will produce three dimensional defects on the surface, and such defects will result non-operational semiconductor devices. Surface imperfections, such as cracks, subsurface damage, pits, particles, scratches or contamination will interrupt the replication of the wafer's crystal structure by the CVD process (see, for example, Powell and Larkin, Phys. Stat. Sol. (b) 202, 529 (1997)). It is important that the polishing and cleaning processes used to fabricate the wafer minimize surface imperfections. In the presence of these surface imperfections several defects can be generated in the epitaxial films including basal plane dislocations and cubic SiC inclusions (see for example, Powell, et. al. Transactions Third International High-Temperature Electronics Conference, Volume 1, pp. II-3-II-8, Sandia National Laboratories, Albuquerque, N. Mex. USA, 9-14 June 1996).
Defects in SiC are known to limit or destroy operation of semiconductor devices formed over the defects. Neudeck and Powell reported that hollow core screw dislocations (micropipes) severely limited voltage blocking performance in SiC diodes (P. G. Neudeck and J. A. Powell, IEEE Electron Device Letters, vol. 15, no. 2, pp. 63-65, (1994)). Neudeck reviewed the impact of crystal (wafer) and epitaxy originated defects on power devices in 1994 highlighting limitations of power device function due to screw dislocations and morphological epitaxy defects (Neudeck, Mat. Sci. Forum, Vols 338-342, pp. 1161-1166 (2000)). Hull reported shift to lower values in the distribution of high voltage diode reverse bias leakage current when the diodes were fabricated on substrates having lower screw dislocation density (Hull, et. al., Mat. Sci. forum, Vol. 600-603, p. 931-934 (2009)). Lendenmann reported forward voltage degradation in bipolar diodes was linked to basal plane dislocations in the epilayer that originate from basal plane dislocations in the substrate (Lendenmann et. al., Mat. Sci. Forum, Vols 338-342, pp. 1161-1166 (2000)). In order to realize the potential performance advantages of SiC devices, the defects in the active device area must be reduced to levels where they are effectively benign.
As most defects originate in the bulk crystal, many researchers have tried to develop epitaxy processes which can inhibit propagation of the defects like basal plane dislocations from the substrate to the epitaxial films. The techniques included chemical etching of the substrate surface prior to CVD growth, strategic alterations to the CVD process and combinations thereof. In the case of propagation of basal plane dislocations from the polished substrate into the epitaxial layers, these dislocations are either converted to threading edge dislocations, which are relatively benign to semiconductor device operation or the basal plane dislocation will extend into the epitaxial layers. Reduction of basal plane dislocations is enhanced by several approaches including lowering the tilt angle of the wafer, altering the polishing process, altering the CVD process parameters. For example US 2009/0114148 A1 teaches that interrupting the CVD process can have a positive impact on reducing the number basal plane dislocations in the epitaxial layer. US2010/0119849 A1 teaches the use of liquid phase epitaxy as a means to suppress defect reduction in the epitaxial layer. US2007/0221614 A1 combines etching and re-polishing of the substrate and epitaxy to suppress basal plane defects in the epitaxial layer. The typical limitation of these and similar techniques is that they do not work simultaneously on all types of defects and, particularly when starting with substrates with high defect density, they to not reduce the defects to levels where they are benign with respect to the performance of the semiconductor device.